PIC18F2550 lettura input digitale

[Riddik89]

salve a tutti, ho da poco iniziato a utilizzare il PIC18F2550, e subito ho notato la quantità impressionante di periferiche di cui è dotato.
Ho scritto un semplice programma per iniziare a prendere confidenza, ma subito ho riscontrato dei problemi nella lettura dei segnali in ingresso (input digitale).
Il codice è un po' noiosetto da leggere, ma vi sarei grato se mi deste qualche dritta.
Ho disattivato (o almeno credo) i comparatori, il modulo PWM e il convertitore A/D.
So che probabilmente sono anche andato a modificare delle opzioni inutili, ma quando uno non sa più dove sbattere la testa fa di tutto.

un grazie a tutti

Codice: Seleziona tutto

#include <xc.h>

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1L
#pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

// CONFIG1H
#pragma config FOSC = INTOSCIO_EC// Oscillator Selection bits (Internal oscillator, port function on RA6, EC used by USB (INTIO))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
#pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = OFF     // CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)

// CONFIG4L
#pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)



#include <pic18f2550.h>




void inizializzazione(void);
void main (void);

void main(void )
{

inizializzazione();


    while(1)
    {
       
       
   
     
        if(LATA0==0)
            LATA1=1;

            if(LATA0==1)
                 LATA1=0;

    }

}



void inizializzazione(void)
{
    TRISA=0b00100101;
    TRISB=0X00;
    TRISC=0X00;


OSCCON=0b11110110;

//            bit 7 IDLEN: Idle Enable bit
//1 = Device enters Idle mode on SLEEP instruction
//0 = Device enters Sleep mode on SLEEP instruction
//bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
//111 = 8 MHz (INTOSC drives clock directly)
//110 = 4 MHz
//101 = 2 MHz
//100 = 1 MHz
//(3)
//
//011 = 500 kHz
//010 = 250 kHz
//001 = 125 kHz
//000 = 31 kHz (from either INTOSC/256 or INTRC directly)
//bit 3 OSTS: Oscillator Start-up Time-out Status bit
//(1)
//(2)
//1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
//0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
//bit 2 IOFS: INTOSC Frequency Stable bit
//1 = INTOSC frequency is stable
//0 = INTOSC frequency is not stable
//bit 1-0 SCS1:SCS0: System Clock Select bits
//1x = Internal oscillator
//01 = Timer1 oscillator
//00 = Primary oscillator



    T0CON=0b11001000;

//            bit 7 TMR0ON: Timer0 On/Off Control bit
//1 = Enables Timer0
//0 = Stops Timer0
//bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
//1 = Timer0 is configured as an 8-bit timer/counter
//0 = Timer0 is configured as a 16-bit timer/counter
//bit 5 T0CS: Timer0 Clock Source Select bit
//1 = Transition on T0CKI pin
//0 = Internal instruction cycle clock (CLKO)
//bit 4 T0SE: Timer0 Source Edge Select bit
//1 = Increment on high-to-low transition on T0CKI pin
//0 = Increment on low-to-high transition on T0CKI pin
//bit 3 PSA: Timer0 Prescaler Assignment bit
//1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
//0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
//bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
//111 = 1:256 Prescale value
//110 = 1:128 Prescale value
//101 = 1:64 Prescale value
//100 = 1:32 Prescale value
//011 = 1:16 Prescale value
//010 = 1:8 Prescale value
//001 = 1:4 Prescale value
//000 = 1:2 Prescale value

ADCON0=0x00;

// bit 7-6 Unimplemented: Read as ?0?
//bit 5-2 CHS3:CHS0: Analog Channel Select bits
//0000 = Channel 0 (AN0)
//0001 = Channel 1 (AN1)
//0010 = Channel 2 (AN2)
//0011 = Channel 3 (AN3)
//0100 = Channel 4 (AN4)
//0101 = Channel 5 (AN5)
//
//0110 = Channel 6 (AN6)
//
//0111 = Channel 7 (AN7)
//1000 = Channel 8 (AN8)
//1001 = Channel 9 (AN9)
//1010 = Channel 10 (AN10)
//1011 = Channel 11 (AN11)
//1100 = Channel 12 (AN12)
//1101 = Unimplemented
//1110 = Unimplemented
//1111 = Unimplemented
//(1,2)
//(1,2)
//(1,2)
//(2)
//(2)
//(2)
//bit 1 GO/DONE
//: A/D Conversion Status bit
//When ADON =
//1:
//1 = A/D conversion in progress
//0 = A/D Idle
//bit 0 ADON: A/D On bit
//1 = A/D converter module is enabled
//0 = A/D converter module is disabled
ADCON1=0b00001111;
//    A/D CONTROL REGISTER 1      bit 7-6 Unimplemented: Read as ?0?
//bit 5 VCFG1: Voltage Reference Configuration bit (V
//REF- source)
//1 = VREF- (AN2)
//0 = VSS
//bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
//1 = VREF+ (AN3)
//0 = VDD
//bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
// VEDI TABELLA DATASHEET P266



CCP1CON=0; //capture/compare/PWM
CCP2CON=0;



CMCON=0b00000111;
//comparator control register
//C2OUT: Comparator 2 Output bit
//When C2INV =
//0:
//1 = C2 VIN+ > C2 VIN0
//=
//C2
//VIN+
//<
//C2
//VIN-
//When C2INV = 1:
//1 = C2 VIN+ < C2 VIN0
//=
//C2
//VIN+
//>
//C2
//VIN-
//bit 6 C1OUT: Comparator 1 Output bit
//When C1INV =
//0:
//1 = C1 VIN+ > C1 VIN0
//=
//C1
//VIN+
//<
//C1
//VIN-
//When C1INV = 1:
//1 = C1 VIN+ < C1 VIN0
//=
//C1
//VIN+
//>
//C1
//VIN-
//bit 5 C2INV: Comparator 2 Output Inversion bit
//1 = C2 output inverted
//0 = C2 output not inverted
//bit 4 C1INV: Comparator 1 Output Inversion bit
//1 = C1 output inverted
//0 = C1 output not inverted
//bit 3 CIS: Comparator Input Switch bit
//When CM2:CM0 =
//110:
//1 =C1 VIN- connects to RA3/AN3/VREF+
//C2 VIN- connects to RA2/AN2/VREF-/CVREF
//0 =C1 VIN- connects to RA0/AN0
//C2 VIN- connects to RA1/AN1
//bit 2-0 CM2:CM0: Comparator Mode bits
//Figure 22-1 shows the Comparator modes and the CM2:CM0 bit settings.
//p275



CVRCON=0x00;
//COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
//bit 7 CVREN: Comparator Voltage Reference Enable bit
//1 =CV
//REF circuit powered on
//0 =CVREF circuit powered down
//bit 6 CVROE: Comparator VREF Output Enable bit
//(1)
//1 =CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
//0 =CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
//bit 5 CVRR: Comparator VREF Range Selection bit
//1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
//0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
//bit 4 CVRSS: Comparator VREF Source Selection bit
//1 = Comparator reference source, CVRSRC = (VREF+) ? (VREF-)
//0 = Comparator reference source, CVRSRC = VDD ? VSS
//bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ? (CVR3:CVR0) ? 15)
//When CVRR =
//1:
//CVREF = ((CVR3:CVR0)/24) ? (CVRSRC)
//When CVRR =
//0:
//CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) ? (CVRSRC)


UCON=0b00010000;

//USB CONTROL REGISTER
/*bit 7 Unimplemented: Read as ?0?
bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0 Unimplemented: Read as ?0?*/


}


PS aggiungo che gli output digitali sembrano funzionare bene (ho fatto lampeggiare dei semplici led).

[Riddik89]

Ho risolto era il mio povero compilatore impazzito.... se sapete come cancellare il post.... grazie